The present invention relates to a semiconductor memory device, especially, to a nonvolatile semiconductor memory device using a ferroelectric capacitor, a method of driving the same, and various systems each having the semiconductor memory device.
In recent years, a nonvolatile memory (FRAM) using a ferroelectric capacitor has received a great deal of attention as one of semiconductor memories. Since the FRAM is advantageous in that it is nonvolatile, the number of times of rewrite access is 1012, the read/write time almost equals that of a DRAM, and it can operate at a low voltage of 3 to 5V, the FRAMs may replace all memory markets. At present, in the Society, 1M bit FRAMs have been reported (H. Koike et al., 1996, IEEE International Solid-State Circuit Conference Digest of Technical Paper, pp. 368-369, February, 1996).
Along with developments, the cell size of the FRAM has been reduced by simplifying and micropatterning the cell structure, as in development of DRAMs, from the SRAM+Shadow Memory structure as initially developed to a 2-transistor/2-capacitor structure. FIG. 1A shows the memory cell of a conventional DRAM having a 1-transistor/1-capacitor structure. FIG. 1B shows the memory cell of a conventional FRAM having a 1-transistor/1-capacitor structure. Reference symbol WL denotes a word line; BL, a bit line; SN, a storage node; and PL, a plate electrode. Clearly, the memory cell of the conventional FRAM having a 1-transistor/1-capacitor structure is now the same as the DRAM having a 1-transistor/1-capacitor structure having a transistor and a capacitor that are series connected.
The FRAM memory cell basically has the same structure as that of the DRAM. The FRAM is different from the DRAM in the following two points.
(1) Although the DRAM uses a dielectric without any spontaneous dielectric polarization as a capacitor, the FRAM uses a ferroelectric capacitor. (2) In the DRAM, the plate electrode at one terminal of the capacitor is fixed at (1/2)Vcc. However, in the FRAM, the plate electrode potential is changed within the range of 0V to Vcc.
For (2), however, the scheme of changing the plate electrode potential is being replaced with a scheme of fixing the plate electrode at (1/2)Vcc.
Therefore, the FRAM equals the DRAM except for (1). The FRAM also has the same cell array structure as that of the DRAM. The FRAM has a folded bit line (BL) structure as shown in FIG. 1C. The minimum cell size at this time is represented as follows:
2Fxc3x974F=8F2
In FIG. 1C, reference symbol MC denotes a memory cell; SA, a sense amplifier; and F, a minimum processing size. {overscore (BL)} and BL in FIG. 1C denote a bit line pair.
The principle of the operation of the FRAM will be briefly described with reference to FIG. 2A and FIG. 2B.
In the DRAM, the cell transistor is turned on, and Vcc or a voltage of 0V is applied to the cell capacitor to write charges, thereby storing store data xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. In reading, the cell transistor is turned on to read out the charges. In the DRAM, the accumulated charges (polarization value [C]) are proportional to the voltage applied across the cell capacitor, as shown in FIG. 2A. For this reason, when the applied voltage becomes 0V due to a leakage current at the p-n junction of the cell transistor or the like, the polarization value also becomes 0 C, and the information is destroyed.
In the FRAM, however, the polarization characteristics have a hysteresis. A case wherein, after power-ON, the plate (PL) voltage is 0V, the storage node (SN) potential is 0V, and data xe2x80x9c0xe2x80x9d has been written in the cell will be considered. Since the plate electrode potential is 0V, and the storage node potential is 0V, the voltage applied to the ferroelectric capacitor is 0V, and the polarization value is at a position D of the remnant polarization (=xe2x88x92Pr) in FIG. 2B. When the memory cell data is to be read out, the bit line (BL) potential is precharged to 0V, the cell transistor is turned on, and the plate electrode voltage is raised to Vcc. Since the bit line capacity is larger than the storage node capacity, a voltage xe2x88x92Vcc is applied between the bit line and the plate electrode. The polarization value changes from the point D to a point C, so that a potential corresponding to the small saturation polarization difference Psxe2x88x92Pr is read out to the bit line.
When data xe2x80x9c1xe2x80x9d has been written in the cell, the voltage xe2x88x92Vcc is applied between the bit line and the plate electrode, as in the above-described case. Accordingly, polarization inversion from a point B to the point C occurs, and charges in a large amount corresponding to Ps+Pr are read out to the bit line.
The reference bit line potential is raised to the potential at which charges corresponding to Ps are read out. In reading the dataxe2x80x9c1xe2x80x9d, a potential difference corresponding to (Ps+Pr)xe2x88x92(Ps)=Pr is generated between the reference bit line and the bit line. In reading the data xe2x80x9c0xe2x80x9d, a potential difference corresponding to (Psxe2x88x92Pr)xe2x88x92(Ps)=xe2x88x92Pr is generated between the reference bit line and the bit line. This result (potential difference) is amplified by the sense amplifier. The readout result is amplified. by the sense amplifier. For the data xe2x80x9c1xe2x80x9d, the bit line is set at Vcc. For the data xe2x80x9c0xe2x80x9d, the bit line is set at 0V.
To rewrite the memory cell data, the plate electrode voltage is lowered to 0V again. At this time, the data xe2x80x9c0xe2x80x9d returns from the point C to the point D at BLxe2x88x92PL=0V, and the data xe2x80x9c1xe2x80x9d returns from the point C to the point D and then polarization-inverted to a point A at BLxe2x88x92PL=Vcc. Thereafter, the cell transistor is turned off. The data xe2x80x9c1xe2x80x9d moves from the point A to the point B when the storage node potential lowers to 0V due to the leakage current and stops at the point B. FIG. 3A shows the series of operations.
The largest difference between the operation of the FRAM and that of the DRAM is as follows. In the FRAM, no data is read out only by turning on the cell transistor and short-circuiting the bit line BL and the storage node SN. No charges are removed unless the direction of polarization is reversed to that for writing the charges between the bit line BL (storage node SN) and the plate electrode PL. Accordingly, a plate electrode operation with a large load capacity is required, and read/write access takes a long time. This is the disadvantage of the FRAM.
To solve this problem, the scheme of fixing the plate electrode potential at (1/2)Vcc is proposed, as described above. FIG. 3B and FIG. 3C show the operations of these schema. In recall after power-ON (on the left side of FIG. 3B and FIG. 3C), the plate electrode PL is precharged to (1/2)Vcc, and the bit line BL is precharged to 0V. The word line WL is selected to turn on the cell transistor. At this time, a voltage of xe2x88x92(1/2)Vcc is applied between the bit line BL and the plate electrode PL. As shown in FIG. 2B, the data xe2x80x9c1xe2x80x9d is polarization-inverted from the point B to the point C, the data xe2x80x9c0xe2x80x9d moves from the point D to the point C without polarization inversion, and the accumulated charges are read out to the bit line BL. The information xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d is read out depending on the presence/absence of polarization inversion. The readout result is amplified by the sense amplifier. For the data xe2x80x9c1xe2x80x9d, the bit line BL is set at Vcc. For the data xe2x80x9c0xe2x80x9d, the bit line BL is set at Vss. A voltage of (1/2)Vcc=BLxe2x88x92PL or a voltage of (xe2x88x921/2)Vcc=BLxe2x88x92PL is applied to the cells. The data xe2x80x9c1xe2x80x9d moves from the point C to the point A, the data xe2x80x9c0xe2x80x9d stays at the point C, and the data is written.
The scheme shown in FIG. 3B slightly differs from that shown in FIG. 3C in the subsequent operation. In FIG. 3B, after the bit line BL is equalized to (1/2)Vcc (more specifically, the data xe2x80x9c1xe2x80x9d moves from the point A to the point B, and the data xe2x80x9c0xe2x80x9d moves from the point C to the point D), the word line WL is closed to return the bit line potential to 0V. Even when the bit line BL is equalized, the data stays at the point B or D, so the data is not destroyed. This operation reversely exploits the characteristics of the ferroelectric capacitor. In FIG. 3C, after the word line WL is closed, the bit line BL is equalized to (1/2)Vcc (more specifically, the data xe2x80x9c1xe2x80x9d stays at the point A, and the data xe2x80x9c0xe2x80x9d stays at the point C). For reading after recall, the charge difference (Psxe2x88x92Pr) between the point A and the point B or between the point C and the point D is used, as in the DRAM (the degradation in the amount of the remnant polarization Pr due to the fatigue caused by polarization inversion in reading is suppressed).
The scheme shown in FIG. 3B or 3C is more advantageous than that shown in FIG. 3A in that the operation speed in access time or cycle time does not degrade unlike the scheme of changing the plate electrode potential, so that a high-speed operation is enabled. On the other hand, the scheme shown in FIG. 3B or 3C is more disadvantageous than that shown in FIG. 3A in that the voltage (coercive voltage Vc) necessary for polarization inversion must be (1/2)Vcc or less (this problem is solved by reducing the size of the ferroelectric film). Additionally, the FRAM has a large disadvantage in that a refresh operation is required, like the DRAM (the refresh operation increases the stand-by current or generates a busy rate).
In the scheme shown in FIG. 3B, the storage node SN of the cell is at (1/2)Vcc in the stand-by state. When the storage node potential becomes lower than (1/2)Vcc due to the leakage current at the p-n junction or the like, the data xe2x80x9c1xe2x80x9d moves from the point B to the point C, and the data is destroyed. Accordingly, the refresh operation must be performed to select the word line WL and write the potential of (1/2)Vcc in the storage node SN every a predetermined period in the stand-by state, as shown on the right side of FIG. 3B.
In the scheme shown in FIG. 3C, the storage node SN is set at Vcc or 0V in the stand-by state. When the storage node potential becomes lower than VCC due to the leakage current at the p-n junction or the like, the data xe2x80x9c1xe2x80x9d moves from the point A to the point B, and then to the point C, and the data is destroyed. In this case, since the normal operation is the same as that of the DRAM, the data is destroyed upon moving to the point B. Accordingly, the refresh operation must be performed to select the word line WL and read/sense/rewrite the data every predetermined period in the stand-by state, like the DRAM, as shown on the right side of FIG. 3C.
In the scheme for driving the plate electrode between 0V and Vdd, a lot of memory cells are connected to the plate electrode, causing a large load capacity and a very long driving time; therefore, as compared with the conventional DRAM, the operations become slow in both access time and cycle time. The scheme for fixing the plate to (1/2)Vdd makes it possible to realize the same access time and cycle time as the DRAM since it does not need to drive the plate having a large load capacity.
However, as shown in FIG. 1B, the conventional memory cell of the FRAM has a structure in which a transistor and a ferroelectric capacitor are series connected in the same manner as the DRAM; therefore, the storage node (SN) becomes a floating state at stand-by after power has been applied. Consequently, when xe2x80x9c1xe2x80x9d data is maintained in the SN, the SN drops to Vss due to the junction leakage at the p-n junction, with the result that cell information is destroyed in the case of the plate electrode fixed to (1/2)Vdd. Therefore, in the (1/2)Vdd cell plate scheme, the refresh operation is required, resulting in the problem of power increase and the difficulty in production due to severe cell specifications.
As described above, the first problem with the conventional FRAM is that it is difficult to simultaneously achieve high-speed operations (PL potential fixed) and the omission of the refresh.
For the conventional DRAMs, various cells are developed to realize a cell size smaller than 8F2. A stacked-type transistor or stacked-type TFT (Thin Film Transistor) is used to realize a size of 4F2, or cell transistors are connected in series, and capacitors are connected between the cell transistors and the plate electrode PL, thereby realizing a size of about 4F2 (NAND cell).
Since the equivalent circuit of the FRAM is basically the same as that of the DRAM, an FRAM having a size of 4F2 can be realized with the same cell structure as that of the DRAM. The FRAM also has the same problems as those of the DRAM. The stacked-type transistor or stacked-type TFT can hardly be realized because the manufacturing process is more complex than that for a conventional planar transistor having a size of 8F2, which can be easily manufactured. In the FRAM, these cells are basically realized as trench cells in which a transistor is formed after the ferroelectric capacitor process. Therefore, the permittivity of the ferroelectric capacitor decreases due to the heat process in the transistor manufacturing process.
The NAND cell can be manufactured using a planar transistor and can have a stack cell structure in which the capacitor is formed after the transistor process. In the NAND cell, however, cell data must be sequentially read out from cells closer to the bit line BL or must be sequentially written in cells farther from the bit line BL. This degrades the random access properties as an important point of a general-purpose memory and allows only block read/write access.
As described above, in the conventional FRAM, when a memory cell having a size of 4F2 smaller than 8F2 is to be realized, the process becomes complex for, e.g., the stacked-type transistor, or the random access properties of a general-purpose memory degrade for, e.g., a NAND cell. Additionally, the conventional FRAM cannot simultaneously realize the high-speed operation of the scheme of fixing the plate electrode potential and omission of the refresh operation.
Consequently, the second problem with the conventional FRAM cell is that it is impossible to simultaneously achieve the following three points: (1) memory cells having a small size of 4F2, (2) planar transistors that are easily manufactured and (3) general-purpose random access function.
Furthermore, in the conventional FRAM, the following problem is also encountered. FIG. 4A shows a stand-by state of a conventional FRAM, FIG. 4B shows an operation of the PL driving scheme, and FIG. 4D shows a locus on a hysteresis curve upon read-out. In the conventional read-out scheme, assuming that the amount of saturation polarization is Ps and the amount of remnant polarization is Pr, xe2x80x9c1xe2x80x9d data is represented by Ps+Pr, and xe2x80x9c0xe2x80x9d data is represented by Psxe2x88x92Pr as shown in FIG. 4D, and the difference represents the amount of signal (half in the case of 1T/1C). However, the ferroelectric capacitor has great dispersion in its paraelectric component due to dispersion in manufacturing processes, etc.; and this degrades the read-out margin to a great degree. For example, in xe2x80x9c1xe2x80x9d data, Psxe2x88x92Pr component within Ps+Pr is a paraelectric component, and in xe2x80x9c0xe2x80x9d data, the entire signal forms a paraelectric component. In particular, in ferroelectric materials such as PZT, since the dielectric constant itself has a great value, causing a great absolute value in dispersion.
FIG. 4C shows a conventional scheme for solving this problem. Upon read-out, PL is raised from Vss to Vdd, and is lowered from Vdd to Vss, and then the sense amplifier is operated so as to amplify the signal. The locus on the hysteresis curve at the time of this read-out operation is shown in FIG. 4E. xe2x80x9c1xe2x80x9d data (point (2)) is once polarity-inverted, and comes to point (1); however, it comes to point (3) by reducing PL. Thus, xe2x80x9c1xe2x80x9d has its paraelectric component cut during the going and returning processes so that only the remnant polarization component: 2Pr is read out to the bit line as a signal. Sine xe2x80x9c0xe2x80x9d data only goes to point (1) from point (3), and then returns to point (3), no signal is read out. Consequently, only polarization component 2Pr, which is free from the paraelectric component with high dispersion, is used as a signal, thereby making it possible to eliminate noise.
However, in this scheme, as shown in FIG. 4C, PL is again raised, and then PL is lowered in order to re-write data; consequently, PL has to be raised and lowered twice, with the result that read/write access and cycle take a very long time as compared with the case shown in FIG. 4B.
As described above, in the conventional FRAM, the first problem is that it is difficult to achieve both of the high-speed operation (PL potential fixed) and the omission of the refresh operation, and the second problem is that it is impossible to simultaneously achieve the following three points: memory cells having a small size of 4F2, planar transistors that are easily manufactured and general-purpose random access function. Moreover, when an attempt is made to suppress dispersion in the paraelectric component of a ferroelectric capacitor, the operation tends to become slow.
Various systems having semiconductor memories have examined replacement of the conventional DRAM with the FRAM. However, such examinations have not reached a practical level yet because of the above-described problems unique to the FRAM.
It is an object of the present invention to provide a semiconductor memory device which can realize a memory cell having a size (e.g., 4F2) smaller than 8F2 without using any stacked-type transistor or the like and also maintain a random access function.
It is another object of the present invention to provide a semiconductor memory device which can simultaneously realize a high-speed operation by fixing the plate potential and the omission of a refresh operation.
It is still another object of the present invention to provide various systems which can improve the system performance by mounting the semiconductor memory device.
It is another object of the present invention to provide a semiconductor memory device which can suppress dispersion in the paraelectric component of a ferroelectric capacitor without causing a reduction in the operation speed.
To solve the above problems, the present invention employs the following arrangements.
(1) A computer system comprises: a microprocessor for performing various arithmetic processing operations; an input/output device connected to the microprocessor to send/receive data to/from an external device; and a semiconductor memory device connected to the microprocessor to store data, wherein the semiconductor memory device includes a plurality of memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to the source terminal and a second terminal connected to the drain terminal, a predetermined number of memory cells are connected in series, and a select transistor is connected to at least one terminal of the series connected portion to constitute a memory cell block, and a plurality of memory cell blocks are arranged to constitute a cell array.
(1-1) The computer system includes a controller for the semiconductor memory device.
(2-1) The computer system includes a volatile RAM.
(1-3) The computer system includes a ROM.
(2) An IC card comprises an IC chip having a semiconductor memory device, wherein the semiconductor memory device includes a plurality of memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to the source terminal and a second terminal connected to the drain terminal, a predetermined number of memory cells are connected in series, and a select transistor is connected to at least one terminal of the series connected portion to constitute a memory cell block, and a plurality of memory cell blocks are arranged to constitute a cell array.
(3) A digital image input system comprises: an image input device for inputting image data; a data compression device for compressing the input image data; a semiconductor memory device for storing the compressed image data; an output device for outputting the compressed image data; and a display device for displaying one of the input image data and the compressed image data, wherein the semiconductor memory device includes a plurality of memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to the source terminal and a second terminal connected to the drain terminal, a predetermined number of memory cells are connected in series, and a select transistor is connected to at least one terminal of the series connected portion to constitute a memory cell block, and a plurality of memory cell blocks are arranged to constitute a cell array.
(3-1) The digital image input system has a function as a digital camera.
(3-2) The digital image input system has a function as a digital video camera.
(4) A memory system comprises: a semiconductor memory device for storing data; and an input/output device connected to the semiconductor memory device to send/receive data to/from an external device, wherein the semiconductor memory device includes a plurality of memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to the source terminal and a second terminal connected to the drain terminal, a predetermined number of memory cells are connected in series, and a select transistor is connected to at least one terminal of the series connected portion to constitute a memory cell block, and a plurality of memory cell blocks are arranged to constitute a cell array.
(4-1) The memory system includes a controller for controlling the semiconductor memory device.
(4-2) Memory information includes images such as cinema, music and instruction, and game software, OA software, OS software, dictionaries, and map information.
(5) A system LSI chip comprises: a core section for performing various processing operations; and a semiconductor memory device for storing data, wherein the semiconductor memory device includes a plurality of memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to the source terminal and a second terminal connected to the drain terminal, a predetermined number of memory cells are connected in series, and a select transistor is connected to at least one terminal of the series connected portion to constitute a memory cell block, and a plurality of memory cell blocks are arranged to constitute a cell array.
(5-1) The core section is an MPU.
(5-2) According to (5-1), the semiconductor memory device is used as a micro-code memory.
(5-3) According to (5-1), the semiconductor memory device is used as an instruction cache memory.
(5-4) According to (5-1), the semiconductor memory device is used as a data cache memory.
(5-5) According to (5-1), the semiconductor memory device is used as a data memory.
(5-6) The core section is an image processing section for performing image processing.
(5-7) According to (5-6), the semiconductor memory device is used as an image data memory.
(5-8) The core section is a logic section for performing various logic calculations.
(5-9) The LSI chip is a logic variable LSI chip.
(5-10) According to (5-9), the semiconductor memory device is used as a logic synthesis information memory.
(5-11) According to (5-9), the semiconductor memory device is used as a logic connection information storage memory.
(5-12) According to (5-9), the semiconductor memory device is used as an interconnection information storage memory.
(6) A mobile computer system comprises: a microprocessor for performing various arithmetic processing operations; an input device connected to the microprocessor to input data; a radio wave sending/receiving device connected to the microprocessor to send/receive data to/from an external device; an antenna connected to the sending/receiving device; a display.device connected to the microprocessor to display necessary information; and a semiconductor memory device connected to the microprocessor to store data, wherein the semiconductor memory device includes a plurality of memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to the source terminal and a second terminal connected to the drain terminal, a predetermined number of memory cells are connected in series, and a select transistor is connected to at least one terminal of the series connected portion to constitute a memory cell block, and a plurality of memory cell blocks are arranged to constitute a cell array.
(6-1) The mobile computer system has a function as a mobile phone.
(6-2) The mobile computer system has a function as a mobile TV phone.
(6-3) The mobile computer system has a function as a mobile TV and a mobile video.
(6-4) The mobile computer system has a function as a mobile computer display.
(7) A semiconductor memory device comprises: a plurality of memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to the source terminal and a second terminal connected to the drain terminal, wherein the plurality of memory cells are arranged to constitute a cell array.
(8) A semiconductor memory device comprises: a plurality of memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to the source terminal and a second terminal connected to the drain terminal, wherein the plurality of memory cells are connected in series to constitute a memory cell block, and a plurality of memory cell blocks are arranged to constitute a cell array.
(9) According to (8), the memory cell block includes a select transistor connected to at least one terminal of the plurality of series connected memory cells.
(9-1) The two terminals of the memory block are connected to adjacent bit lines, respectively.
(9-2) According to (9-1), the adjacent bit lines constitute a bit line pair and are connected to a sense amplifier.
(9-3) According to (9-1) and (9-2), the select transistor is constituted by a plurality of select transistors connected in series.
(10) A semiconductor memory device comprises: a plurality of memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to the source terminal and a second terminal connected to the drain terminal, wherein the plurality of memory cells are connected in series, and a select transistor is connected to at least one terminal of the series connected portion to constitute a memory cell block, one terminal of the memory cell block is connected to a bit line, and the other terminal is connected to a plate electrode.
(10-1) An open bit line structure is formed by a bit line pair of adjacent cell arrays.
(10-2) One-bit information is stored in two memory cells connected to two bit lines of the same cell array, and a folded bit line structure is formed by a bit line pair.
(10-3) In the stand-by state after power-ON, all the plurality of transistors in the memory block are in ON state, and the select transistor is in OFF state.
(10-4) In selecting an arbitrary memory cell in the memory block, the select transistor is turned on while turning off the transistor of the selected cell, and keeping the transistors of the remaining cells ON.
(10-5) The plate electrode potential is fixed at (1/2)Vcc or a constant voltage after power-ON in both the stand-by state and active state. In addition, no cell data refresh operation is performed.
(10-6) The plate electrode potential is set at 0V in the stand-by state after power-ON and changed within the range of 0V and Vcc in reading/writing data from/into selecting a cell.
(10-7) The bit line is precharged to 0V before cell data is read out.
(10-8) The bit line is precharged to Vcc before cell data is read out.
(10-9) The dummy cell has the same circuit structure as that of the memory cell in the memory block.
(10-10) The capacitor area of the dummy cell is 1.5 to 3 times larger than that of a normal cell.
(10-11) The dummy cell uses a paraelectric capacitor.
(10-12) The ferroelectric capacitor of each memory cell is constituted by connecting a plurality of ferroelectric capacitors in parallel.
(10-13) The ferroelectric capacitor of each memory cell is constituted by connecting a plurality of ferroelectric capacitors having different thicknesses in parallel.
(10-14) The ferroelectric capacitor of each memory cell is constituted by connecting a plurality of ferroelectric capacitors having different coercive voltages in parallel.
(10-15) The ferroelectric capacitor of each memory cell is constituted by connecting a plurality of ferroelectric capacitors and at least one capacitor and p-n junction voltage drop element.
(10-16) The ferroelectric capacitor of each memory cell is constituted by connecting a plurality of ferroelectric capacitors and at least one resistance element.
(10-17) The ferroelectric capacitor of each memory cell is constituted by connecting a first ferroelectric capacitor and a resistance element in series, and connecting a second ferroelectric capacitor to the series connected elements in parallel.
(10-18) According to (10-12) to (10-17), each of the plurality of ferroelectric capacitors of each memory cell stores 1-bit information.
(10-19) According to (10-14) and (10-15), each of the plurality of ferroelectric capacitors of each memory cell stores 1-bit information, and 1-bit data is read out from or written in each of the plurality of ferroelectric capacitors by changing the voltage to be applied to the ferroelectric capacitor.
(10-20) According to (10-14) and (10-15), each of the plurality of ferroelectric capacitors of each memory cell stores 1-bit information. In reading, a low voltage is applied to the ferroelectric capacitor to read out polarization charges of one of the plurality of ferroelectric capacitors, and the readout information is stored outside the cell array. Next, the applied voltage is raised to read out polarization charges of one of the remaining ferroelectric capacitors. In writing, the voltage is sequentially lowered and applied to the ferroelectric capacitors in an opposite order to that in reading, thereby performing writing.
(10-21) According to (10-12) to (10-17), the sense amplifier has a temporary storage memory.
(10-22) According to (10-13), the difference in thickness among the ferroelectric capacitors is preferably 3 or more times.
(10-23) According to (10-14), the difference in coercive voltage among the ferroelectric capacitors is preferably 3 or more times.
(11) According to (10), wherein the select transistors includes first and second select transistors connected in series.
(11-1) An open bit line structure is formed by a bit line pair of adjacent cell arrays.
(11-2) A bit line pair of the same cell array are used to turn on only the first and second select transistors connected to one of the two bit lines in reading/writing cell data, thereby forming a folded bit line structure.
(11-3) In the stand-by state after power-ON, all the plurality of transistors in the memory blocks are ON, and one of the first and second select transistors is OFF.
(11-4) In selecting an arbitrary memory cell in the memory block, both the first and second select transistor are turned on while turning off the transistor of the selected cell, and keeping the transistors of the remaining cells ON.
(11-5) The plate electrode potential is fixed at (1/2)Vcc or a constant voltage after power-ON in both the stand-by state and active state. In addition, no cell data refresh operation is performed.
(11-6) The plate electrode potential is set at 0V in the stand-by state after power-ON and changed within the range of 0V and Vcc in reading/writing data in selecting a cell.
(11-7) The bit line is precharged to 0V before cell data is read out.
(11-8) The bit line is precharged to Vcc before cell data is read out.
(11-9) The dummy cell has the same circuit structure as that of the memory cell in the memory block.
(11-10) The capacitor area of the dummy cell is 1.5 to 3 times larger than that of a normal cell.
(11-11) The dummy cell uses a paraelectric capacitor.
(11-12) The ferroelectric capacitor of each memory cell is constituted by connecting a plurality of ferroelectric capacitors in parallel.
(11-13) The ferroelectric capacitor of each memory cell is constituted by connecting a plurality of ferroelectric capacitors having different thicknesses in parallel.
(11-14) The ferroelectric capacitor of each memory cell is constituted by connecting a plurality of ferroelectric capacitors having different coercive voltages in parallel.
(11-15) The ferroelectric capacitor of each memory cell is constituted by connecting a plurality of ferroelectric capacitors and at least one voltage drop element.
(11-16) The ferroelectric capacitor of each memory cell is constituted by connecting a plurality of ferroelectric capacitors and at least one resistance element.
(11-17) The ferroelectric capacitor of each memory cell is constituted by connecting a first ferroelectric capacitor and a resistance element in series, and connecting a second ferroelectric capacitor to the series connected elements in parallel.
(11-18) According to (11-12) to (11-17), each of the plurality of ferroelectric capacitors of each memory cell stores 1-bit information.
(11-19) According to (11-12) to (11-15), each of the plurality of ferroelectric capacitors of each memory cell stores 1-bit information, and 1-bit data is read out from or written in each of the plurality of ferroelectric capacitors by changing the voltage to be applied to the ferroelectric capacitor.
(11-20) According to (11-13) and (11-14), each of the plurality of ferroelectric capacitors of each memory cell stores 1-bit information. In reading, a low voltage is applied to the ferroelectric capacitor to read out polarization charges of one of the plurality of ferroelectric capacitors, and the readout information is stored outside the cell array. Next, the applied voltage is raised to read out polarization charges of one of the remaining ferroelectric capacitors. In writing, the voltage is sequentially lowered and applied to the ferroelectric capacitors in an opposite order to that in reading, thereby performing writing.
(11-21) According to (11-12) to (11-17), the sense amplifier has a temporary storage memory.
(11-22) According to (11-13), the difference in thickness among the ferroelectric capacitors is preferably 3 or more times.
(11-23) According to (11-14), the difference in coercive voltage among the ferroelectric capacitors is preferably 3 or more times.
(12) According to (10), the select transistors includes first to fourth select transistors connected in series, one terminal of each of two memory cell blocks is connected to the same bit line, and the other terminal is connected to the plate electrode.
(12-1) A bit line pair of the same cell array are used to turn on all of four series connected select transistors only in one of four cell blocks connected to the bit line pair in reading/writing cell data, thereby forming a folded bit line structure.
(12-2) In the stand-by state after power-ON, all the plurality of transistors in the memory block are ON, and one of the first to fourth select transistors are OFF.
(12-3) In selecting an arbitrary memory cell in the memory block, all the first to fourth select transistors are turned on while turning off the transistor of the selected cell, and keeping the transistors of the remaining cells ON.
(12-4) The plate electrode potential is fixed at (1/2)Vcc or a constant voltage after power-ON in both the stand-by state and active state. In addition, no cell data refresh operation is performed.
(12-5) The plate electrode potential is set at 0V in the stand-by state after power-ON and changed within the range of 0V and Vcc in reading/writing data in selecting a cell.
(12-6) The bit line pitch is twice the cell pitch.
(12-7) The dummy cell has the same circuit structure as that of the memory cell in the memory block.
(12-8) The capacitor area of the dummy cell is 1.5 to 3 times larger than that of a normal cell.
(12-9) The dummy cell uses a paraelectric capacitor.
(12-10) The ferroelectric capacitor of each memory cell is constituted by connecting a plurality of ferroelectric capacitors in parallel.
(12-11) The ferroelectric capacitor of each memory cell is constituted by connecting a plurality of ferroelectric capacitors having different thicknesses in parallel.
(12-12) The ferroelectric capacitor of each memory cell is constituted by connecting a plurality of ferroelectric capacitors having different coercive voltages in parallel.
(12-13) The ferroelectric capacitor of each memory cell is constituted by connecting a plurality of ferroelectric capacitors and at least one voltage drop element.
(12-14) The ferroelectric capacitor of each memory cell is constituted by connecting a plurality of ferroelectric capacitors and at least one resistance element.
(12-15) The ferroelectric capacitor of each memory cell is constituted by connecting a first ferroelectric capacitor and a resistance element in series, and connecting a second ferroelectric capacitor to the series connected elements in parallel.
(12-16) According to (12-10) to (12-15), each of the plurality of ferroelectric capacitors of each memory cell stores 1-bit information.
(12-17) According to (12-10) to (12-13), each of the plurality of ferroelectric capacitors of each memory cell stores 1-bit information, and 1-bit data is read out from or written in each of the plurality of ferroelectric capacitors by changing the voltage to be applied to the ferroelectric capacitor.
(12-18) According to (12-10) and (12-13), each of the plurality of ferroelectric capacitors of each memory cell stores 1-bit information. In reading, a low voltage is applied to the ferroelectric capacitor to read out polarization charges of one of the plurality of ferroelectric capacitors, and the readout information is stored outside the cell array. Next, the applied voltage is raised to read out polarization charges of one of the remaining ferroelectric capacitors. In writing, the voltage is sequentially lowered and applied to the ferroelectric capacitors in an opposite order to that in reading, thereby performing writing.
(12-19) According to (12-10) to (12-15), the sense amplifier has a temporary storage memory.
(12-20) According to (12-11), the difference in thickness among the ferroelectric capacitors is at least 3 or more times.
(12-21) According to (12-12), the difference in coercive voltage among the ferroelectric capacitors is at least 3 or more times.
(13) A semiconductor memory device comprises: a plurality of memory cells, the memory cell being constituted by a first transistor having a source terminal and a drain terminal, a first ferroelectric capacitor which has a first terminal connected to the source terminal of the first transistor and a second terminal connected to the drain terminal and stores first data, a second transistor connected in series to the first transistor, and a second ferroelectric capacitor which is connected in parallel to a series connected portion of the first and second transistors and stores second data, the memory cell storing 2-bit data, wherein the plurality of memory cells are connected in series, and one or more select transistors are connected to at least one terminal of the series connected portion to constitute a memory cell block, and a plurality of memory cell blocks are arranged to constitute a cell array.
(14) According to any one of (7) to (14), a dummy cell in a dummy cell block corresponding to a memory cell block has a transistor, and a ferroelectric or paraelectric capacitor connected between a source and drain terminals of the transistor, the dummy cell block is constituted by connecting a plurality of dummy cells in series and connecting at least one first and at least one second select transistors connected in series to one terminal of the series connected portion, the other terminal of the first select transistor is connected to a first bit line, and the other terminal of the second select transistor is connected to a second bit line.
(14-1) An area of a capacitor of the dummy cell is 1.5 to 3 or more times.
(15) A method of driving a semiconductor memory device which comprises a plurality of memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to the source terminal and a second terminal connected to the drain terminal, a predetermined number of memory cells being connected in series to constitute a memory cell block, and has a random access function, comprises the steps of: the first step of turning on transistors of the plurality of memory cells in the memory cell block; and the second step of setting a transistor of any one of the plurality of memory cells in the memory cell block in an OFF state to select the memory cell, and writing/reading data in/from the selected cell.
(16) A method of driving a semiconductor memory device which comprises a plurality of memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to the source terminal and a second terminal connected to the drain terminal, a predetermined number of memory cells being connected in series to constitute a memory cell block, and has a random access function, comprises the steps of: the first step of turning on transistors of the plurality of memory cells in the memory cell block; the second step of setting a transistor of any one of the plurality of memory cells in the memory cell block in an OFF state to select the memory cell, and applying, to the selected memory cell, a voltage higher than a first minimum coercive voltage of coercive voltages of the ferroelectric capacitors, thereby reading out information stored in the ferroelectric capacitor having the first coercive voltage; the third step of writing a voltage higher than the first coercive voltage in the selected memory cell; the fourth step of applying a voltage higher than a second coercive voltage higher than the first coercive voltage to the selected memory cell, thereby reading out information stored in the ferroelectric capacitor having the second coercive voltage; and the fifth step of writing a voltage higher than the second coercive voltage in the selected memory cell.
(16-1) Reading/writing of data is performed in the order of the first step, the second step, the fourth step, the fifth step, the third step, and the first step.
(16-2) Writing of data is performed in the order of the first step, the fifth step, the third step, and the first step.
As a method of manufacturing a semiconductor memory device of the present invention, the following arrangement is preferably employed.
(1) Ferroelectric capacitors are formed after formation of cell transistors, and thereafter, bit lines are formed.
(2) Bit lines are formed after formation of cell transistors, and thereafter, ferroelectric capacitors are formed.
(3) In formation of the ferroelectric capacitor, a ferroelectric film is formed on a lower electrode, and an upper electrode is formed on the resultant structure.
(4) The lower electrode of the ferroelectric capacitor contains Pt, Ti, and the like.
(5) The ferroelectric capacitor contains Bi, Sr, Ta, O, and the like, Pb, Zr, Ti, O, and the like, or Ba, Sr, Ti, O, and the like.
(6) The electrode of the ferroelectric capacitor contains Ir or IrO2, or Si, Ru, O, and the like.
(7) For the lower electrode of the ferroelectric capacitor, an Si plug is formed on a diffusion layer, and a Ti/TiN/Pt layer is formed on the resultant structure.
(8) A TiO2 layer is formed on the upper electrode of the ferroelectric capacitor, and an SiO2 layer is formed on the resultant structure.
(9) The ferroelectric capacitor has a single crystal structure.
(10) The lattice constants of the ferroelectric capacitor and the upper or lower electrode are different from each other, so that a distortion is generated therebetween.
(11) Electrode nodes at the two terminals of the ferroelectric capacitor are simultaneously formed, and the ferroelectric film is formed between the two electrode nodes. The ferroelectric film is formed by CVD or MOCVD.
(12) The ferroelectric film is formed in a direction perpendicular or parallel to the wafer surface.
In the present invention, the following arrangement is preferable.
(1) A plurality of ferroelectric capacitor layers are stacked on the Si surface.
(2) The memory cell transistor is a depletion-type transistor.
(3) According to (2), in the stand-by state or power-OFF state, the potential of a word line as the gate of the cell transistor is 0V.
(4) In turning on the power supply, a negative potential is applied to the substrate.
(5) A substrate bias generation circuit for applying a negative potential to the substrate in turning on the power supply is formed on the chip.
(6) In turning on the power supply, the word line potential is applied, and then the plate potential is raised to (1/2)Vcc.
(7) In turning off the power supply, the plate potential is lowered to 0V, and then the word line potential is lowered to 0V.
(8) In turning off the power supply, the plate potential is lowered to 0V, and then the word line potential is lowered to 0V. Thereafter, the power supply is turned off.
(9) Four electrode layers contacting the source/drain diffusion layer of the cell transistor are stacked above the word line. The first and third layers are connected. A capacitor is formed between the second electrode layer and a layer formed by the first and third electrode layers. Another capacitor is formed between the third and fourth electrode layers.
(10) The bit line consists of W, Al or Cu.
(11) The bit line is arranged between adjacent ferroelectric capacitors along the word line.
(12) The bit line is formed under the ferroelectric capacitor.
(13) The bit line is formed above the ferroelectric capacitor.
(14) The upper electrode of the ferroelectric capacitor is connected to the source or drain terminal of the cell transistor through an Al interconnection.
(15) A PL (plate) electrode of the normal cell is changed in a range of 0V to Vcc, and a PL of the dummy cell is fixed to Vcc/2 or a constant voltage.
(16) The plate electrode is changed in a constant voltage range.
(17) The plate electrode is snapped by the Al or Cu wiring.
The following advantages are obtained in accordance with the above arrangement.
The conventional FRAM has a structure as an extension of the conventional DRAM. In the present invention, the cell transistor and the ferroelectric capacitor are connected in parallel, unlike the prior art using a series connected structure. In addition, in the present invention, a plurality of memory cells are connected in series, one terminal of the series connected cells is connected to the plate electrode, and the other terminal is connected to the bit line through the select transistor.
With this structure, in the stand-by state, the gate of the cell transistor is ON, and two terminals of the ferroelectric capacitor are short-circuited because of the parallel connection and set at an equipotential. According to the conventional DRAM concept, this structure absolutely destroys accumulated information. In the ferroelectric memory, however, data is not destroyed even when the potential difference between the storage node SN and the plate electrode is set at 0V. That is, charges are not read out unless the polarization direction is reversed to that for writing. The present invention conversely exploits this unique problem of the FRAM as an advantage.
In the present invention, in the stand-by state, the two terminals of the ferroelectric capacitor are always short-circuited regardless of the operation of fixing the plate potential or changing the plate potential within the range of 0V to Vcc. Even in case of a leakage current at the p-n junction or the like, the potential difference between the two terminals of the ferroelectric capacitor is 0V, and charges corresponding to the remnant polarization amount are kept held. No polarization inversion occurs, so the data is not destroyed. Even when the cutoff current of the cell transistor or the leakage current of the ferroelectric capacitor has a large value, the cell information is not destroyed. As a result, a highspeed operation can be performed while fixing the plate potential, and simultaneously the refresh operation can be omitted, unlike the prior art.
A case wherein one of the plurality of series connected cells is to be selected will be considered. Assume that, from four series connected cells, the second cell from the plate electrode, i.e., the third cell from the bit line is to be selected. In this case, only the cell transistor of the selected memory cell is turned off, and the select transistor is turned on. The first, third, and fourth cell transistors from the plate electrode are equivalently kept ON. For this reason, one terminal of the ferroelectric capacitor of the selected memory cell is electrically connected to the plate electrode, and the other terminal is electrically connected to the bit line. Apparently, in the circuit of the present invention, the cell transistor of the conventional ferroelectric memory corresponds to the select transistor, and the ferroelectric capacitor directly corresponds to the ferroelectric capacitor. Therefore, the present invention can cope with both the conventional scheme of fixing the plate electrode at (1/2)Vcc and the scheme of changing the plate electrode potential within the range of 0V to Vcc.
When data is to be read/written in selecting the second memory cell from the plate electrode, the cell transistors of the unselected cell, i.e., the first, third, and fourth cells from the plate electrode are ON, and the potential between the two terminals of the ferroelectric capacitor is set at 0V, so the cell data is not destroyed. As a result, in the present invention, although the memory cells are connected in series, data can be read/written from/into an arbitrary cell. Not block access as in the conventional NAND cell but perfect random access is enabled.
In the conventional NAND cell, when the number of series connected cells increases, the bit line capacity can be decreased. However, when the number of series connected cells is too large, and data is to be read out from a cell far from the bit line, the bit line capacity increases by an amount corresponding to other cell capacities from the bit line to the target read cell. This conversely increases the bit line capacity.
In the present invention, however, the number of series connected cells can be considerably increased, and the bit line capacity can be largely decreased. This is because the two terminals of the ferroelectric capacitor of an unselected cell are short-circuited, and the capacity of the ferroelectric capacitor does not electrically appear. In addition, when the gate of the select transistor is connected to a signal line different from that of the gate of a select transistor connected to the other one of the bit line pair, no cell data is read out to the reference bit line, so that a folded bit line structure capable of reducing noise can be realized. As described above, according to the present invention, random read/write access is enabled, the bit line capacity can be decreased, and the array noise can be reduced.
For the cell structure, the gate of the cell transistor can be formed in the minimum processing size (F), and the diffusion layer and the active region for channel formation can be formed in the minimum processing size (F). Therefore, a planar transistor which can be easily manufactured can be used, and the cell size can be reduced to a size represented as follows:
2Fxc3x972F=4F2.
The ferroelectric capacitor is formed by extracting source and drain electrodes of the cell transistor upward from the diffusion layer region between the gates after formation of the transistor. One of the electrodes is used as the lower electrode of the ferroelectric capacitor, and the other is used as the upper electrode of the ferroelectric capacitor. With this structure, the ferroelectric capacitor can be connected in parallel to the cell transistor in a stack structure.
The above effects will be summarized. In the conventional nonvolatile FRAM, facilitation of manufacturing and realization of high integration cannot be simultaneously realized while maintaining the random access function, like the conventional DRAM. However, the present invention can simultaneously realize all these functions. In addition, reduction of the bit line capacity and noise reduction are also enabled. Furthermore, the high-speed operation can be maintained while employing the scheme of fixing the plate potential at (1/2)Vcc, and simultaneously, the refresh operation can be omitted, although it is impossible in the conventional FRAM.
When the semiconductor memory device of the present invention is applied to various systems such as a computer system, an IC card, a digital image input system, a memory system, a system LSI chip, and a mobile computer system, the performance of each system can be improved using the advantages of the semiconductor memory device. More specifically, the semiconductor memory device of the present invention can omit the refresh operation and perform a high-speed operation, and also increase the density. Therefore, the semiconductor memory device can be applied to a high-speed system having low power consumption, or a high-speed system which requires a high-temperature operation. The semiconductor memory device can also be applied to a system in a heavy stress environment or a system which requires a large-capacity memory.
As has been described above in detail, according to the present invention, the transistor and the ferroelectric capacitor are connected in parallel to constitute a memory cell of the FRAM. With this structure, a memory cell having a size (e.g., 4F2) smaller than 8F2 without using any stacked-type transistor can be realized, and simultaneously, the random access function can be maintained.
In addition, using the scheme of fixing the plate potential at (1/2)Vcc, a high-speed operation as in the DRAM can be maintained, and simultaneously, the refresh operation can be omitted.
Furthermore, the bit line capacity can be decreased. In modifications, noise reduction, relaxation of the bit line rule or sense amplifier rule, reduction of the number of sense amplifiers, an increase in readout signal amount, and storage of multi-bit data in a cell with a size of 4F2 are enabled.
The ferroelectric memory of the present invention can operate at a high speed and omit the refresh operation. Therefore, the ferroelectric memory can be applied to a high-speed system having low power consumption, or a high-speed system which requires a high-temperature operation. The semiconductor memory device can also be applied to a system which requires a high density in a heavy stress environment or a system which requires a large-capacity memory.
Moreover, another structure of the present invention is described as follows:
(1) A semiconductor memory device comprises: a plurality of memory cells each having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to the source terminal, wherein the plurality of memory cells are connected in series, and one or more selected transistors connected to at least one terminal of the series connected memory cells to constitute a memory cell block, the memory cell block having one terminal connected to a bitline and another terminal connected to a plate electrode, and wherein two memory cell blocks, which are respectively connected to two bit lines forming a bit line pair and also connected to the same word line, are respectively connected to a first plate electrode and a second plate electrode.
(2) A gate electrode of the transistor is connected to the word lines, and a predetermined number of the memory cell blocks are arranged in a word-line direction to constitute a cell block unit; the first plate electrode and second plate electrode are connected to the memory cell blocks of the cell block unit alternately for every one or for every two memory cell blocks. Where, the first and second plate electrodes are respectively connected to two memory cell blocks which are connected to the same bit line.
With the structure in the above-mentioned (1) and (2), by dividing a PL line, in the 1T/1C structure, even if the PL driving scheme is adopted, a block select transistor is not turned on while being connected to the selected word line and the PL line connected to a cell block from which no cell data is read is not driven; therefore, the potential of the floating node within the cell block from which no cell data is read does not change so that no reduction in polarization data occurs.
(3) A semiconductor memory device comprises: a memory cell constituted by parallel-connecting a ferroelectric capacitor between source and drain terminals of a transistor; and a memory cell block constituted by series-connecting the plural memory cells, with at least one end of the series connected portion being connected to a select transistor, one end of the memory cell block being connected to a bit line, the other end being connected to a plate electrode, wherein, at stand-by after application of power, the plate electrode is set at Vss and the bit line is set at Vdd or High level.
(4) A semiconductor memory device comprises: a memory cell constituted by parallel-connecting a ferroelectric capacitor between source and drain terminals of a transistor; and a memory cell block constituted by series-connecting the plural memory cells, with at least one end of the series connected portion being connected to a select transistor, one end of the memory cell block being connected to a bit line, the other end being connected to a plate electrode, wherein, at stand-by after application of power, the plate electrode is set at Vdd or High level and the bit line is set at Vss.
With the structure of the above-mentioned (3) and (4), upon active operation, the difference between the PL potential and the BL potential has already been set at Vdd; therefore, only by turning the word line OFF and turning the block selection line ON, the polarization information of the cell is read out by the bit line, and when PL is raised (or lowered) once, the paraelectric component having dispersion can be cancelled, thereby making it possible to improve the reading reliability. Then, after amplified by a sense amplifier, PL is lowered (or raised), thereby completing the re-writing process of cell data. Therefore, only by raising (or lowering) PL once, it is possible to cancel the paraelectric component having dispersion, thereby making it possible to simultaneously realize the high-speed operation and high reliability.
(5) A semiconductor memory device comprises: a memory cell constituted by parallel-connecting a ferroelectric capacitor between source and drain terminals of a transistor; a memory cell block constituted by series-connecting the plural memory cells, with at least one end of the series connected portion being connected to a select transistor, one end of the memory cell block being connected to a bit line, the other end being connected to a plate electrode; and a memory cell array constituted by arranging the plural memory cell blocks, each cell being provided with a write-in buffer for writing data from external portion, wherein the write-in buffer consists of a first writein transistor having a small size and a second write-in transistor having a large size, and upon writing data, the time at which the second write-in transistor is started to be driven is set slower than the time at which the first write-in transistor is started to be driven.
With the structure of the above-mentioned (5), since the writing speed is slow, noise at the time of writing, which is inherently caused in the ferroelectric capacitor, can be reduced.
(6) A semiconductor memory device comprises: a plurality of memory cells each having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to the source terminal, wherein the plurality of memory cells are connected in series, and one or more selected transistors connected to at least one terminal of the series connected memory cells to constitute a memory cell block, the memory cell block having one terminal connected to a bitline and another terminal connected to a plate electrode, and wherein a wiring of the plate electrode is formed by the same metal wiring layer such as Al and Cu that constitutes a wiring for connecting the cell transistor and the ferroelectric capacitor of the memory cell.
With the structure of the above-mentioned (6), the PL wire is formed by using the metal wire connecting the cell transistor and the ferroelectric capacitor; therefore, the resistance in the PL wire is reduced and RC delay in the PL wire in the PL driving scheme can be shortened.
(7) A semiconductor device comprises: a plurality of memory cells each having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to the source terminal and a second terminal connected to the drain terminal, and a gate electrode of the cell transistor connected to a word line, wherein the plurality of memory cells are connected in series, and one or more selected transistors connected to at least one terminal of the series connected memory cells to constitute a memory cell block, the memory cell block having one terminal connected to a bitline and another terminal connected to a plate electrode, and wherein a metal wiring layer connected with the plate electrode via a contact hole is the same layer as metal wiring layer connected with the word line via a contact hole with predetermined interval.
With the structure of the above-mentioned (7), the PL wire is formed by using the metal wire for use in ward line snap; therefore, the resistance in the PL wire is reduced and RC delay in the PL wire in the PL driving scheme can be shortened.
(8) A semiconductor memory device comprises: a plurality of memory cells each having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to the source terminal, wherein the plurality of memory cells are connected in series, and one or more selected transistors connected to at least one terminal of the series connected memory cells to constitute a memory cell block, the memory cell block having one terminal connected to a bitline and another terminal connected to a plate electrode, and wherein a driving circuit for driving the plate electrode is placed in a bit line direction for every one or for every two memory cell blocks.
With the structure of the above-mentioned (8), it is possible to allow the plate-line driving transistor in the plate-line driving circuit to have a large size, the ON resistance of the transistor is reduced, and RC delay in the PL wire in the PL driving scheme can be shortened.
(9) A semiconductor memory device comprises: a memory cell constituted by parallel-connecting an nMOS transistor, a PMOS transistor and a ferroelectric capacitor; and a memory cell block constituted by series-connecting at least one selection switch constituted by series-connecting the plural memory cells with at least one end of the series connected portion being parallel-connected to the nMOS transistor and PMOS transistor, one end of the memory cell block being connected to a bit line, the other end being connected to a plate electrode.
With the structure of the above-mentioned (9), the memory transistor and the block select transistor are fully formed by CMOS, voltage drop at the threshold value is eliminated, the data read/write operations are carried out without raising the voltage of the word line and the block selection line to not less than Vdd, the voltage-raising circuit is eliminated, and it becomes possible to improve the reliability and also to allow for mixed installation, etc.
Here, the following arrangements are listed as preferred modes for carrying out the present invention.
(a) In (1) and (2), in one cycle during an active operation, only either the first plate electrode or the second electrode is operated between Vss and Vdd, while the other remains at Vss.
(b) In (2), the first and second plate electrodes are respectively shared by the memory cell block adjacent thereto in the bit-line direction.
(c) In (3), in one cycle upon operation, the plate electrode drops from Vss to Vdd or High level of the bit line only once, and returns to Vss.
(d) In (4), in one cycle upon operation, the plate electrode drops from Vdd or High level of the bit line to Vss only once, and returns to Vdd or High level of the bit line.
(e) In (3) and (4), the ferroelectric capacitor of the memory cell is constituted by parallel connecting two or more ferroelectric capacitors having different coercive voltages.
(f) In (6), the metal wiring layer is placed as a top layer after formation of the upper electrode and the lower electrode of the ferroelectric capacitor, and the upper electrode and the lower electrode are connected with a contact interpolated in between.
(g) In (7), the contact gap between the first metal wiring layer and the plate wiring layer is set at every 1 bit line, every two bit lines, every four bit lines, or every word line snap gap.
As described above in detail, the present invention makes it possible to provide the following advantages: easy production is available by using nonvolatile planar transistors, high integrity having a size of 4F2 is realized with random access properties, and (1) in the 1TilC type, the plate driving scheme is adopted, which makes it possible to carry out a high-density operation with low voltage. Moreover, (2) high-speed operation is achieved while suppressing dispersion in the paraelectric component in the ferroelectric capacitor. Furthermore, (3) noise at the time of writing is reduced. (4) High-speed operation is achieved in the plate driving scheme while reducing process costs and chip sizes. (5) Since cells are formed by using CMOS, it is possible to eliminate voltage raising processes to the word line and the block selection line.
A semiconductor memory device may comprise: a plurality of memory cells each having a first transistor having a first source terminal and a first drain terminal and a ferroelectric capacitor having a first terminal connected to the firs source terminal and a second terminal connected to the first drain terminal, wherein the plurality of memory cells are connected in series; and a dummy cell having a second transistor having a second source terminal and a second drain terminal and a ferroelectric capacitor or paraelectric capacitor having a third terminal connected to the second source terminal and a fourth terminal connected to the second drain terminal.
Additional objects and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention. The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.